ENRICHING WSN ENVIRONMENT WITH CONTEXT INFORMATION

Currently the Internet of Things environment suffer from a variety of uniqueproblems such as low throughput, inadequate support for mobility and notcompatible(and often close) application environments. However, characteristicof physical environment often provides opportunities to address these problems.This paper explores concepts of enriching the WNS environment withcontext-based information. By context we consider all data available in sensorsenvironment, not only data processed by them. Currently this data are not utilizedby sensors, but we think that they can improve overall functionality of thesensor network. We also discuss the practical challenges facing the integrationof such an approach into the sensor application stack

Software controlled low cost thermoelectric energy harvester for ultra-low power wireless sensor nodes

General hardware architecture of an energy-harvested wireless sensor network node (EH-WSN) can be divided into power, sensing, computing and communication subsystems. Interrelation between these subsystems in combination with constrained energy supply makes design and implementation of EH-WSN a complex and challenging task. Separation of these subsystems into distinct hardware modules simplifies the design process and makes the architecture and software more generic, leading to more flexible solutions. From the other hand, tightly coupling these subsystems gives more room for optimizations at the price of increased complexity of the hardware and software. Additional engineering effort could be justified by a smaller, cheaper hardware, and more energy-efficient a wireless sensor node. The aim of this paper is to push further technical and economical boundaries related to EH-WSN by proposing a novel architecture which – by tightly coupling software and hardware of power, computing, and communication subsystems – allows the wireless sensor node to be powered by a thermoelectric generator working with about 1.5°C temperature difference while keeping the cost of all electronic components used to build such a node below 9 EUR (in volume)

Prediction of Functional Sites Based on the Fuzzy Oil Drop Model

A description of many biological processes requires knowledge of the 3-D structure of proteins and, in particular, the defined active site responsible for biological function. Many proteins, the genes of which have been identified as the result of human genome sequencing, and which were synthesized experimentally, await identification of their biological activity. Currently used methods do not always yield satisfactory results, and new algorithms need to be developed to recognize the localization of active sites in proteins. This paper describes a computational model that can be used to identify potential areas that are able to interact with other molecules (ligands, substrates, inhibitors, etc.). The model for active site recognition is based on the analysis of hydrophobicity distribution in protein molecules. It is shown, based on the analyses of proteins with known biological activity and of proteins of unknown function, that the region of significantly irregular hydrophobicity distribution in proteins appears to be function related

FatPaths: Routing in Supercomputers and Data Centers when Shortest Paths Fall Short

We introduce FatPaths: a simple, generic, and robust routing architecture that enables state-of-the-art low-diameter topologies such as Slim Fly to achieve unprecedented performance. FatPaths targets Ethernet stacks in both HPC supercomputers as well as cloud data centers and clusters. FatPaths exposes and exploits the rich ("fat") diversity of both minimal and non-minimal paths for high-performance multi-pathing. Moreover, FatPaths uses a redesigned "purified" transport layer that removes virtually all TCP performance issues (e.g., the slow start), and incorporates flowlet switching, a technique used to prevent packet reordering in TCP networks, to enable very simple and effective load balancing. Our design enables recent low-diameter topologies to outperform powerful Clos designs, achieving 15% higher net throughput at 2x lower latency for comparable cost. FatPaths will significantly accelerate Ethernet clusters that form more than 50% of the Top500 list and it may become a standard routing scheme for modern topologies

A High-Performance Design, Implementation, Deployment, and Evaluation of The Slim Fly Network

Novel low-diameter network topologies such as Slim Fly (SF) offer significant cost and power advantages over the established Fat Tree, Clos, or Dragonfly. To spearhead the adoption of low-diameter networks, we design, implement, deploy, and evaluate the first real-world SF installation. We focus on deployment, management, and operational aspects of our test cluster with 200 servers and carefully analyze performance. We demonstrate techniques for simple cabling and cabling validation as well as a novel high-performance routing architecture for InfiniBand-based low-diameter topologies. Our real-world benchmarks show SF's strong performance for many modern workloads such as deep neural network training, graph analytics, or linear algebra kernels. SF outperforms non-blocking Fat Trees in scalability while offering comparable or better performance and lower cost for large network sizes. Our work can facilitate deploying SF while the associated (open-source) routing architecture is fully portable and applicable to accelerate any low-diameter interconnect

Network-on-Multi-Chip (NoMC) with Monitoring and Debugging Support, Journal of Telecommunications and Information Technology, 2011, nr 3

This paper summarizes recent research on network-on-multi-chip (NoMC) at Poznań University of Technology. The proposed network architecture supports hierarchical addressing and multicast transition mode. Such an approach provides new debugging functionality hardly attainable in classical hardware testing methodology. A multicast transmission also enables real-time packet monitoring. The introduced features of NoC network allow to elaborate a model of hardware video codec that utilizes distributed processing on many FPGAs. Final performance of the designed network was assessed using a model of AVC coder and multi-FPGA platforms. In such a system, the introduced multicast transmission mode yields overall gain of bandwidth up to 30%. Moreover, synthesis results show that the basic network components designed in Verilog language are suitable and easily synthesizable for FPGA devices